Guest Editor's Introduction: What is Infrastructure IP?

0740-7475/02/$17.00 © 2002 IEEE May–June 2002 Every new node of semiconductor technology provides further miniaturization and higher performance, increasing the number of advanced functions that electronic products can offer. Although adding such advanced functions can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies of 0.13 micron and below have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. These new defect levels require enhanced detection, test, diagnosis, and yield optimization solutions. Factory infrastructure (external equipment) alone is insufficient to handle such solutions; a supplemental on-chip support infrastructure is needed. To address this challenge, semiconductor IP providers have introduced embedded intellectual-property blocks, called infrastructure IP, and designers have incorporated these IP blocks into system-on-a-chip (SoC) designs. This D&T special issue covers a range of infrastructure IP for embedded test, yield optimization, timing measurement, debugging, repair, diagnosis, and robustness. Two sidebars (“The silicon infrastructure opportunity” and “The 70-nm silicon challenge”) set the stage with perspectives from two key analysts. Six articles then analyze key trends in manufacturing susceptibility and field reliability that necessitate the use of such IP. The first article, by ARM’s Teresa McLaurin and Souvik Ghosh, describes a dedicated infrastructure IP for test and diagnosis functions. This infrastructure IP uses an IEEE proposed standard, P1500, which allows accessibility to individual functional-IP blocks, such as processors and other interface cores. Designers implement this basic infrastructure IP around the peripheries of individual embedded cores. Today, increasing time-to-market pressures on semiconductor fabrication often force foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. To optimize the design and possibly modify the process to obtain better yield, foundries should diagnose yield problems during the early development cycles of a new manufacturing process. Collecting the information needed for yield optimization will require the inclusion of waferor chip-level specialized infrastructure IP. An article by HPL Technologies’ Jim Bordelon et al. presents such an infrastructure IP solution, currently used as a diagnostic test vehicle to monitor and collect specific device attributes. This information feeds analysis and modification capabilities to optimize yield. Besides the infrastructure IP blocks for test, diagnosis, and yield optimization, another chip level infrastructure IP might be required to help measure timing specifications. Because these specifications are often very stringent in today’s SoCs, external instrumentation is not enough; embedded timing-analysis IP can help. In their article, Sassan Tabatabaei from Vector 12 and André Ivanov from the University of British Columbia describe an infrastructure IP that achieves effective accuracy. This IP distributes multiple probes over different parts of a SoC to collect the necessary timing information. A central IP core controls the probes and transfers the information to a timing processor for analysis. Another process that necessitates infrastructure IP is silicon debugging for verification. Today’s trends of miniaturization and increasing numbers of metal layers make silicon debugging more necessary than ever. Conventional debugging processes using external equipment, such as physical or electron-beam probing, have become insufficient. An embedded infrastructure, with its corresponding software tools, is necGuest Editor’s Introduction: What is Infrastructure IP?